cpu_regs.h File Reference

Definitions for bits in the CPU special registers. More...

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Namespaces
namespace	cpu_reg
	Contains definitions for bits in the CPU special registers.
Enumerations
enum	cpu_reg::EflagsBits
	Bits in x86 EFLAGS register. More...
enum	cpu_reg::Cr0Bits {   cpu_reg::CR0_PE = 0x00000001, cpu_reg::CR0_MP = 0x00000002, cpu_reg::CR0_EM = 0x00000004, cpu_reg::CR0_TS = 0x00000008,   cpu_reg::CR0_PG = 0x80000000, cpu_reg::CR0_NE = 0x00000020, cpu_reg::CR0_WP = 0x00010000, cpu_reg::CR0_AM = 0x00040000,   cpu_reg::CR0_NW = 0x20000000, cpu_reg::CR0_CD = 0x40000000 }
	Bits in x86 CR0 register. More...
enum	cpu_reg::Cr4Bits {   cpu_reg::CR4_VME = 0x00000001, cpu_reg::CR4_PVI = 0x00000002, cpu_reg::CR4_TSD = 0x00000004, cpu_reg::CR4_DE = 0x00000008,   cpu_reg::CR4_PSE = 0x00000010, cpu_reg::CR4_PAE = 0x00000020, cpu_reg::CR4_MCE = 0x00000040, cpu_reg::CR4_PGE = 0x00000080,   cpu_reg::CR4_PCE = 0x00000100, cpu_reg::CR4_FXSR = 0x00000200, cpu_reg::CR4_XMM = 0x00000400, cpu_reg::CR4_VMXE = 0x00002000,   cpu_reg::CR4_SMXE = 0x00004000, cpu_reg::CR4_PCDIE = 0x00020000 }
	Bits in x86 CR4 (starting from PPro) special registers. More...
enum	cpu_reg::CpuidBits { , cpu_reg::CPUID_EFEAT_SYSCALL = (1 << 11), cpu_reg::CPUID_EFEAT_NX = (1 << 20), cpu_reg::CPUID_EFEAT_RDTSCP = (1 << 27), cpu_reg::CPUID_EFEAT_IA64 = (1 << 29) }
	Bits in values returned by cpuid instruction. More...
enum	cpu_reg::MsrRegs
	Model-specific registers for the i386 family. More...
enum	cpu_reg::Ia32eferBits { cpu_reg::IA32_EFER_SCE = 0x001, cpu_reg::IA32_EFER_LME = 0x100, cpu_reg::IA32_EFER_LMA = 0x400, cpu_reg::IA32_EFER_NXE = 0x800 }
	Bits in x86 IA32_EFER MSR. More...
enum	cpu_reg::ApicBaseBits
	Bits in x86 IA32_APIC_BASE MSR. More...
enum	cpu_reg::PatModes
	x86LatEntrymodes. More...
enum	cpu_reg::MtrrConsts
	Constants related to x86 MTRRs.
enum	cpu_reg::Pcr0Bits { ,   cpu_reg::PCR0_RSTK = 0x01, cpu_reg::PCR0_BTB = 0x02, cpu_reg::PCR0_LOOP = 0x04, cpu_reg::PCR0_AIS = 0x08,   cpu_reg::PCR0_MLR = 0x10, cpu_reg::PCR0_BTBRT = 0x40, cpu_reg::PCR0_LSSER = 0x80 }
	Performance Control Register (5x86 only). More...
enum	cpu_reg::DirRegs
	x86 Device Identification Registers
enum	cpu_reg::McRegConsts
	x86 Machine Check register constants. More...
enum	cpu_reg::NcrConsts
	The following four 3-byte registers control the non-cacheable regions. More...
enum	cpu_reg::ArrConsts
	The address region registers are used to specify the location and size for the eight address regions. More...
enum	cpu_reg::RcrConsts { ,   cpu_reg::RCR_RCD = 0x01, cpu_reg::RCR_RCE = 0x01, cpu_reg::RCR_WWO = 0x02, cpu_reg::RCR_WL = 0x04,   cpu_reg::RCR_WG = 0x08, cpu_reg::RCR_WT = 10, cpu_reg::RCR_NLB = 20 }
	The region control registers specify the attributes associated with the ARRx address regions. More...

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Detailed Description

Definitions for bits in the CPU special registers.