Contains definitions for bits in the CPU special registers. More...

Enumerations
enum	EflagsBits
	Bits in x86 EFLAGS register. More...
enum	Cr0Bits { CR0_PE = 0x00000001, CR0_MP = 0x00000002, CR0_EM = 0x00000004, CR0_TS = 0x00000008, CR0_PG = 0x80000000, CR0_NE = 0x00000020, CR0_WP = 0x00010000, CR0_AM = 0x00040000, CR0_NW = 0x20000000, CR0_CD = 0x40000000 }
	Bits in x86 CR0 register. More...
enum	Cr4Bits { CR4_VME = 0x00000001, CR4_PVI = 0x00000002, CR4_TSD = 0x00000004, CR4_DE = 0x00000008, CR4_PSE = 0x00000010, CR4_PAE = 0x00000020, CR4_MCE = 0x00000040, CR4_PGE = 0x00000080, CR4_PCE = 0x00000100, CR4_FXSR = 0x00000200, CR4_XMM = 0x00000400, CR4_VMXE = 0x00002000, CR4_SMXE = 0x00004000, CR4_PCDIE = 0x00020000 }
	Bits in x86 CR4 (starting from PPro) special registers. More...
enum	CpuidBits { , CPUID_EFEAT_SYSCALL = (1 << 11), CPUID_EFEAT_NX = (1 << 20), CPUID_EFEAT_RDTSCP = (1 << 27), CPUID_EFEAT_IA64 = (1 << 29) }
	Bits in values returned by cpuid instruction. More...
enum	MsrRegs
	Model-specific registers for the i386 family. More...
enum	Ia32eferBits { IA32_EFER_SCE = 0x001, IA32_EFER_LME = 0x100, IA32_EFER_LMA = 0x400, IA32_EFER_NXE = 0x800 }
	Bits in x86 IA32_EFER MSR. More...
enum	ApicBaseBits
	Bits in x86 IA32_APIC_BASE MSR. More...
enum	PatModes
	x86LatEntrymodes. More...
enum	MtrrConsts
	Constants related to x86 MTRRs.
enum	Pcr0Bits { , PCR0_RSTK = 0x01, PCR0_BTB = 0x02, PCR0_LOOP = 0x04, PCR0_AIS = 0x08, PCR0_MLR = 0x10, PCR0_BTBRT = 0x40, PCR0_LSSER = 0x80 }
	Performance Control Register (5x86 only). More...
enum	DirRegs
	x86 Device Identification Registers
enum	McRegConsts
	x86 Machine Check register constants. More...
enum	NcrConsts
	The following four 3-byte registers control the non-cacheable regions. More...
enum	ArrConsts
	The address region registers are used to specify the location and size for the eight address regions. More...
enum	RcrConsts { , RCR_RCD = 0x01, RCR_RCE = 0x01, RCR_WWO = 0x02, RCR_WL = 0x04, RCR_WG = 0x08, RCR_WT = 10, RCR_NLB = 20 }
	The region control registers specify the attributes associated with the ARRx address regions. More...

Detailed Description

Contains definitions for bits in the CPU special registers.

Enumeration Type Documentation

enum cpu_reg::ApicBaseBits

Bits in x86 IA32_APIC_BASE MSR.

enum cpu_reg::ArrConsts

The address region registers are used to specify the location and size for the eight address regions.

ARRx + 0: A31-A24 of start address
ARRx + 1: A23-A16 of start address
ARRx + 2: A15-A12 of start address | ARR_SIZE_xx

enum cpu_reg::CpuidBits

Bits in values returned by cpuid instruction.

Enumerator:

CPUID_EFEAT_SYSCALL	SYSCALL/SYSRET available (when in 64-bit mode.
CPUID_EFEAT_NX	Execute Disable Bit available.
CPUID_EFEAT_RDTSCP	RDTSCP and IA32_TSC_AUX are available if 1.
CPUID_EFEAT_IA64	Intel(c) 64 Architecture available if 1.

enum cpu_reg::Cr0Bits

Bits in x86 CR0 register.

Enumerator:

CR0_PE	Protected mode Enable.
CR0_MP	"Math" (FPU) Present
CR0_EM	EMulate FPU instructions. (trap ESC only)
CR0_TS	Task Switched (if MP, trap ESC and WAIT)
CR0_PG	PaGing enable.
CR0_NE	Numeric Error enable (EX16 vs IRQ13)
CR0_WP	Write Protect (honor page protect in all modes)
CR0_AM	Alignment Mask (set to enable AC flag)
CR0_NW	Not Write-through.
CR0_CD	Cache Disable.

enum cpu_reg::Cr4Bits

Bits in x86 CR4 (starting from PPro) special registers.

Enumerator:

CR4_VME	Virtual 8086 Mode Extensions.
CR4_PVI	Protected-mode Virtual Interrupts.
CR4_TSD	Time Stamp Disable.
CR4_DE	Debugging Extensions.
CR4_PSE	Page Size Extensions.
CR4_PAE	Physical Address Extension.
CR4_MCE	Machine Check Enable.
CR4_PGE	Page Global Enable.
CR4_PCE	Performance monitoring Counter Enable.
CR4_FXSR	Fast FPU Save/Restore used by OS.
CR4_XMM	Enable SIMD/MMX2 to use except 16.
CR4_VMXE	VMX-Enable.
CR4_SMXE	SMX-Enable.
CR4_PCDIE	Enables process-context identifiers.

enum cpu_reg::EflagsBits

Bits in x86 EFLAGS register.

enum cpu_reg::Ia32eferBits

Bits in x86 IA32_EFER MSR.

Enumerator:

IA32_EFER_SCE	SysCall enable.
IA32_EFER_LME	IA-32e mode enable.
IA32_EFER_LMA	IA-32e mode active.
IA32_EFER_NXE	Execute-disable bit enable.

enum cpu_reg::McRegConsts

x86 Machine Check register constants.

enum cpu_reg::MsrRegs

Model-specific registers for the i386 family.

enum cpu_reg::NcrConsts

The following four 3-byte registers control the non-cacheable regions.

These registers must be written as three separate bytes.

NCRx+0: A31-A24 of starting address
NCRx+1: A23-A16 of starting address
NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.

The non-cacheable region's starting address must be aligned to the size indicated by the NCR_SIZE_xx field.

enum cpu_reg::PatModes

x86LatEntrymodes.

enum cpu_reg::Pcr0Bits

Performance Control Register (5x86 only).

Enumerator:

PCR0_RSTK	Enables return stack.
PCR0_BTB	Enables branch target buffer.
PCR0_LOOP	Enables loop.
PCR0_AIS	Enables all instructions stalled to serialize pipe.
PCR0_MLR	Enables reordering of misaligned loads.
PCR0_BTBRT	Enables BTB test register.
PCR0_LSSER	Disable reorder.

enum cpu_reg::RcrConsts

The region control registers specify the attributes associated with the ARRx address regions.

Enumerator:

RCR_RCD	Disables caching for ARRx (x = 0x0,-6).
RCR_RCE	Enables caching for ARR7.
RCR_WWO	Weak write ordering.
RCR_WL	Weak locking.
RCR_WG	Write gathering.
RCR_WT	Write-through.
RCR_NLB	LBA# pin is not asserted.

Enumerations

Detailed Description

Enumeration Type Documentation